//`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module MutMiso(
	input				clk_in,//100M时钟
	input				rst_n,
	input				rd_en,
	output	reg			CS,
	output	reg			SPI_SCLK,
	input				SPI_SDI,
	output	reg			SPI_SDO,

	input		[15:0]	CMD,		//读数地址
	output	reg	[31:0]	DATA1		//数据1
);

localparam	READY		= 4'd1;
localparam	IDLE		= 4'd2;
localparam	data_CMD	= 4'd3;
localparam	SCLK_L		= 4'd4;
localparam	data_DATA1	= 4'd5;
localparam	OVER1		= 4'd7;
localparam	OVER 		= 4'd8;

reg[3:0] state/*synthesis noprune*/;
reg[1:0] cnt_4;
reg[7:0] cnt_CMD;
reg[7:0] cnt_data1;
reg[7:0] cnt_data2;
reg[7:0] cnt_OVER1;

reg[31:0] DATA11;
reg[4:0] cnt_8;
reg[4:0] cnt_5;
reg[7:0] SCLK_LL;


reg en_0,en_1;
wire en_pos;
assign en_pos = (!en_1) && (en_0);  /* 取上升沿 */
always @(posedge clk_in or negedge rst_n) begin
	if (!rst_n) begin
		{en_1,en_0} <= 2'b00;
	end else begin
		{en_1,en_0} <= {en_0,rd_en};
	end
end

always @(posedge clk_in or negedge rst_n) begin
	if (!rst_n) begin
		CS			<= 1'b1;
		DATA11		<= 32'd0;
		state		<= READY;
		cnt_5		<= 5'd0;
		cnt_CMD		<= 8'd15;
		cnt_data1	<= 8'd34;
		cnt_data2	<= 8'd31;
		cnt_OVER1	<= 8'd2;
		SPI_SDO		<= 1'b0;
		SCLK_LL		<= 8'd0;
	end else begin
		case (state)
			READY: begin
				if (en_pos) begin
					CS			<= 1'b0;
					state		<= IDLE;
					DATA11  	<= 32'd0;
					SPI_SDO 	<= 1'b0;
					SCLK_LL 	<= 8'd0;
				end else begin
					CS			<= 1'b1;
					state		<= READY;
					DATA11  	<= 32'd0;
					SPI_SDO 	<= 1'b0;
				end
			end
			IDLE: begin
				state		<= data_CMD;
				CS			<= 1'b0;
				cnt_CMD	 	<= 8'd15;
				cnt_data1	<= 8'd34;
				cnt_data2 	<= 8'd1;
				cnt_OVER1 	<= 8'd2;
				SPI_SDO	 	<= 1'b0;
			end
			data_CMD: begin
				if (cnt_4 == 2'd0) begin
					if (cnt_CMD > 8'd0) begin
						SPI_SDO	<= CMD[cnt_CMD];
						cnt_CMD	<= cnt_CMD - 8'd1;
					end else begin
						SPI_SDO	<= CMD[0];
						state	<= SCLK_L;
					end
				end else begin
					state		<= data_CMD;
				end
			end
			SCLK_L: begin
				if (SCLK_LL > 8'd5) begin
					SCLK_LL <= 8'd0;
					state 	<= data_DATA1;
				end else if (SCLK_LL == 8'd3) begin
					state 	<= SCLK_L;
					SCLK_LL <= SCLK_LL + 8'd1;
					SPI_SDO <= 1'b0;
				end else begin
					SCLK_LL <= SCLK_LL + 8'd1;
					state	<= SCLK_L;
				end
			end
			data_DATA1: begin
				if (cnt_4 == 2'd2) begin
					if (cnt_data1 > 8'd0) begin
						DATA11[cnt_data1]	<= SPI_SDI;
						cnt_data1 			<= cnt_data1 - 8'd1;
					end else begin
						DATA11[0]			<= SPI_SDI;
						state				<= OVER;
					end
				end else begin
					state		<= data_DATA1;
				end
			end
			// OVER1: begin
			// 	if (cnt_4 == 2'd2) begin
			// 		if (cnt_OVER1 > 8'd0) begin
			// 			DATA1		<= DATA11;
			// 			cnt_OVER1	<= cnt_OVER1 - 8'd1;
			// 		end else begin
			// 			state	<= OVER;
			// 			CS		<= 0;
			// 		end
			// 	end else begin
			// 		state		<= OVER1;
			// 	end
			// end
			OVER: begin
				if (cnt_5 == 5'd4) begin
					CS		<= 1'b1;
					state	<= READY;
					cnt_5	<= 5'd0;
				end else begin
					DATA1	<= DATA11;
					cnt_5	<= cnt_5 + 5'd1;
					CS		<= 1'b0;
					state	<= state;
				end
			end
			default: begin
				state	<= READY;
				DATA11	<= 32'd0;
				CS		<= 1'b1;
				SPI_SDO	<= 1'b0;
			end
		endcase
	end
end

always @(posedge clk_in or negedge rst_n) begin
	if (!rst_n) begin
		SPI_SCLK	<= 1'b0;
	end else if (cnt_4 == 2'd0) begin
		SPI_SCLK	<= 1'b1;
	end else if (cnt_4 == 2'd2) begin
		SPI_SCLK	<= 1'b0;
	end else begin
		SPI_SCLK	<= SPI_SCLK;
	end
end

always @(posedge clk_in or negedge rst_n) begin
	if (!rst_n) begin
		cnt_4	<= 2'd2;
	end else if (state == data_CMD) begin
		cnt_4	<= cnt_4 + 1'b1;
	end else if (state == SCLK_L) begin
		cnt_4	<= 2'd2;
	end else if (state == data_DATA1) begin
		cnt_4	<= cnt_4 + 1'b1;
	end else if (state == OVER1) begin
		cnt_4	<= cnt_4 + 1'b1;
	end else begin
		cnt_4	<= 2'd2;
	end
end


endmodule

